Semiconductor processing and packaging techniques are continually evolving to meet industry demands for improved performance and reduced size and cost. Electronic products require packaged semiconductor assemblies with a high density of devices in a relatively small space. For example, the space available for memory devices, processors, displays and other microfeature devices is continually decreasing in cell phones, personal digital assistants, laptop computers and many other products. Accordingly, a need exists to increase the density of semiconductor devices and components within the confined footprint of the semiconductor assembly. One technique to increase the density of semiconductor devices within a given footprint is to stack packaged semiconductor devices. A challenge with this technique, however, is providing adequate electrical interconnects within and between the stacked packages.
Conventional interconnects electrically connect the integrated circuitry of a semiconductor device (such as a die) with other devices. For example, wire bonds and stud bumps can be used to electrically connect semiconductor devices to a lead frame and/or a support substrate. Interconnects within a device or package can also be formed by creating a via in the device and then filling or plugging the via with conductive material. FIG. 1 illustrates an existing interconnect 100 including a filled via 110. The via 110 is formed by drilling or etching a hole through a silicon wafer 112. The interconnect 100 is then formed by depositing a conductive layer 114 in and around the via 110, and patterning the conductive layer 114 external to the via 110 to isolate the conductive layer 114 and provide an appropriate electrical signal route. The remaining void in the via 110 is filled with a conductive fill material 116. The conductive layer 114 and the conductive fill material 116 electrically connect a pad 117 at a first side of the package with a solder ball 118 (or other conductive feature) at a second side of the package.
One challenge associated with forming the interconnect 100 illustrated in FIG. 1 is that it may be difficult to achieve uniform metallization in the via. If the metallization within the via is non-uniform, the quality and integrity of the interconnect can decrease. For example, vias having a high aspect ratio (i.e., ratio of the depth to the width of the opening) are especially difficult to consistently plate and fill. Moreover, in certain circumstances the filling process can trap air in the via that can cause the interconnect or assembly to crack as the fill material and the assembly harden. Such non-uniformities in the metallization of the via can result in inconsistent electrical connections and compromise the integrity of the interconnects.
Other challenges associated with existing interconnects are the cost, time and complexity of forming, plating and filling the vias. Forming the vias by an ablation or drilling process typically requires forming individual vias in a sequential manner, which increases the processing time required to form the vias. Simultaneously forming the vias by an etching process can be much faster, but etching can result in vias having inconsistent sizes. It can also be difficult to achieve a dense distribution of the vias with an etching process. Moreover, the plating and filling steps following the via formation require additional processing time. Accordingly, a need exists to improve interconnects and processes for forming interconnects in packaged semiconductor devices and assemblies.